1. Field of the Invention
This invention relates generally to the manufacture of high density, high performance semiconductor devices. More specifically, this invention relates to the manufacture of high density, high performance semiconductor devices utilizing a reduced number of steps during the manufacturing process.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacture must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of devices per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the throughput of the fabrication facility (the xe2x80x9cfabxe2x80x9d).
A single semiconductor chip requires numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. As can be appreciated, a reduction in the number of process steps in which the semiconductor wafers must be moved from one tool to another can be a major increase in the throughput of the tab as well as a major decrease in the cost of manufacturing the chips on the semiconductor wafer.
Therefore, what is needed are methods of reducing the number of processing steps necessary to manufacture semiconductor wafers on which semiconductor integrated chips are manufactured.
According to the present invention, the foregoing and other objects and advantages are obtained by a method of manufacturing a semiconductor memory device that reduces the number of manufacturing steps required to manufacture the device.
In accordance with an aspect of the invention, the method includes the following sequence of steps; core, n-channel and p-channel transistors are formed in a semiconductor substrate, source and drain DDI (double diffused implant) implants are simultaneously formed for the core transistors, source and drain Mdd (modified drain diffusion) implants are formed for the core transistors, source and drain Pldd (P lightly doped drain) implants for the p-channel transistors, source and drain Nldd (N lightly doped drain) implants are formed for the n-channel transistors, sidewall spacers are formed on the core, p-channel and n-channel transistors, N+ implants are formed for the n-channel transistors and P+ implants are formed for the p-channel transistors.
In accordance with another aspect of the invention, P+ contact implants are formed for the p-channel transistors.
The described method thus provides a method for reducing the number of manufacturing steps required to manufacture a semiconductor memory device.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.